lpddr5_system
Top-level system model for the LPDDR5 hardware architecture.
Lpddr5System
Bases: SystemBase
Coordinates the connection of all sub-components and defines the overall system layout for LPDDR5.
Source code in src/ecc_analyzer/models/lpddr5/lpddr5_system.py
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configure_system()
Defines the hierarchical structure of the LPDDR5 system.
Constructs the main DRAM processing chain (Sources -> SEC -> TRIM -> BUS -> LINK -> SEC-DED -> TRIM) and merges it with other hardware components.
Source code in src/ecc_analyzer/models/lpddr5/lpddr5_system.py
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