Index
Exposes the LPDDR5 specific hardware components and system model.
BusTrim
Bases: Base
Component for trimming and distributing failure rates across the bus architecture.
This module injects specific bus-related fault sources (AZ) and redistributes SBE, DBE, and TBE faults for both SPFM and LFM paths based on LPDDR5 specifications.
Source code in src/ecc_analyzer/models/lpddr5/bus_trim.py
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__init__(name)
Initializes the BusTrim component with bus-specific split parameters.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/bus_trim.py
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configure_blocks()
Configures the root block as a collection of fault injections and split operations.
Uses a SumBlock to aggregate the source injection (AZ) and the parallel redistribution (SplitBlocks) of incoming faults.
Source code in src/ecc_analyzer/models/lpddr5/bus_trim.py
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DramTrim
Bases: Base
Handles the redistribution of SBE, DBE, and TBE faults for both residual and latent paths.
This component uses a SumBlock to apply parallel split operations that redistribute fault rates according to specific hardware trimming factors defined for LPDDR5.
Source code in src/ecc_analyzer/models/lpddr5/dram_trim.py
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__init__(name)
Initializes the DramTrim component with hardware-specific split distribution parameters.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/dram_trim.py
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configure_blocks()
Configures the root block as a collection of split operations.
Each split block redistributes the specified fault type according to the defined ratios. Both SPFM (residual) and LFM (latent) paths are processed in parallel.
Source code in src/ecc_analyzer/models/lpddr5/dram_trim.py
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Events
Bases: Base
Initializes the baseline DRAM failure rates for LPDDR5.
This module acts as a primary source for SBE, DBE, MBE, and WD faults. As a pure source component, it uses a SumBlock to inject all rates in parallel.
Source code in src/ecc_analyzer/models/lpddr5/events.py
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__init__(name)
Initializes the fault rates based on a baseline DRAM FIT value.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/events.py
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configure_blocks()
Configures the internal block structure by injecting failure rates as basic events.
Uses a SumBlock as these faults occur independently and in parallel on the hardware level.
Source code in src/ecc_analyzer/models/lpddr5/events.py
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LinkEcc
Bases: Base
Component for the Link ECC interface.
This block models the transmission errors on the interface (Source) and the corresponding Error Correction Code (Coverage) that mitigates these errors.
Source code in src/ecc_analyzer/models/lpddr5/link_ecc.py
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__init__(name)
Initializes the LinkEcc component.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/link_ecc.py
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configure_blocks()
Configures the root block as a sequential pipeline.
Using a PipelineBlock ensures that the faults generated by the BasicEvent (Source) are immediately processed by the CoverageBlock (ECC).
Source code in src/ecc_analyzer/models/lpddr5/link_ecc.py
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Lpddr5System
Bases: SystemBase
Coordinates the connection of all sub-components and defines the overall system layout for LPDDR5.
Source code in src/ecc_analyzer/models/lpddr5/lpddr5_system.py
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configure_system()
Defines the hierarchical structure of the LPDDR5 system.
Constructs the main DRAM processing chain (Sources -> SEC -> TRIM -> BUS -> LINK -> SEC-DED -> TRIM) and merges it with other hardware components.
Source code in src/ecc_analyzer/models/lpddr5/lpddr5_system.py
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OtherComponents
Bases: Base
Component representing miscellaneous hardware parts that contribute a fixed FIT rate.
This module encapsulates all non-DRAM components (e.g., peripheral logic) into a single source injection block to simplify the top-level model.
Source code in src/ecc_analyzer/models/lpddr5/other_components.py
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__init__(name)
Initializes the component and sets the constant source FIT rate.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/other_components.py
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configure_blocks()
Configures the root block to inject the FIT rate.
Uses a SumBlock as the base container for the fault source (BasicEvent). The fault is injected into the residual path (is_spfm=True).
Source code in src/ecc_analyzer/models/lpddr5/other_components.py
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Sec
Bases: Base
Component for Single Error Correction (SEC) in LPDDR5.
This module handles SBE coverage (correcting single bit errors) and redistributes DBE failure rates (Double Bit Errors splitting into TBE). It also introduces a latent Single Bit (SB) fault source.
Source code in src/ecc_analyzer/models/lpddr5/sec.py
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__init__(name)
Initializes the SEC component.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/sec.py
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configure_blocks()
Configures the root block.
Combines latent fault injection (SB) with parallel processing of incoming SBE (Coverage) and DBE (Split) faults using a SumBlock.
Source code in src/ecc_analyzer/models/lpddr5/sec.py
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SecDed
Bases: Base
Component for Single Error Correction and Double Error Detection (SEC-DED).
This module handles the diagnostic coverage for multiple fault types (SBE, DBE, TBE, MBE) and manages the transformation of Triple Bit Errors (TBE) into Multi Bit Errors (MBE).
Source code in src/ecc_analyzer/models/lpddr5/sec_ded.py
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__init__(name)
Initializes the SEC-DED component with coverage and source parameters.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/sec_ded.py
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configure_blocks()
Configures the block structure.
Uses a SumBlock to combine the latent fault source (SDB) with the main processing pipeline (Split & Coverage).
Source code in src/ecc_analyzer/models/lpddr5/sec_ded.py
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SecDedTrim
Bases: Base
Component for trimming and distributing residual and latent fault rates after SEC-DED processing.
This module chains sequential split operations for SBE, DBE, and TBE fault types to model the final trimming behavior of the LPDDR5 architecture.
Source code in src/ecc_analyzer/models/lpddr5/sec_ded_trim.py
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__init__(name)
Initializes the SecDedTrim component with predefined split parameters.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name
|
str
|
The descriptive name of the component. |
required |
Source code in src/ecc_analyzer/models/lpddr5/sec_ded_trim.py
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configure_blocks()
Configures the root block as a collection of split operations.
Redistributes faults for both residual (SPFM) and latent (LFM) paths.
Source code in src/ecc_analyzer/models/lpddr5/sec_ded_trim.py
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