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lpddr4_system

Top-level system model for the LPDDR4 hardware architecture.

Lpddr4System

Bases: SystemBase

Coordinates the connection of all sub-components and defines the overall system layout.

Source code in src/ecc_analyzer/models/lpddr4/lpddr4_system.py 
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class Lpddr4System(SystemBase):
    """
    Coordinates the connection of all sub-components and defines the overall system layout.
    """

    def configure_system(self):
        """
        Defines the hierarchical structure of the LPDDR4 system.
        Constructs the main DRAM processing chain and merges it with other hardware components.
        """
        main_chain = PipelineBlock(
            "DRAM_Path",
            [
                Events("Source"),
                Sec("SEC"),
                DramTrim("TRIM"),
                BusTrim("BUS"),
                SecDed("SEC-DED"),
                SecDedTrim("SEC-DED-TRIM"),
            ],
        )

        self.system_layout = SumBlock(self.name, [main_chain, OtherComponents("Other_HW")])

configure_system()

Defines the hierarchical structure of the LPDDR4 system. Constructs the main DRAM processing chain and merges it with other hardware components.

Source code in src/ecc_analyzer/models/lpddr4/lpddr4_system.py 
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def configure_system(self):
    """
    Defines the hierarchical structure of the LPDDR4 system.
    Constructs the main DRAM processing chain and merges it with other hardware components.
    """
    main_chain = PipelineBlock(
        "DRAM_Path",
        [
            Events("Source"),
            Sec("SEC"),
            DramTrim("TRIM"),
            BusTrim("BUS"),
            SecDed("SEC-DED"),
            SecDedTrim("SEC-DED-TRIM"),
        ],
    )

    self.system_layout = SumBlock(self.name, [main_chain, OtherComponents("Other_HW")])